The Phase Lock Loop Unit (PLLU) ( Part # 3530-40 ) is an option board which generates a 32.768MHz clock synchronized to 1.544MHz from the T1 interface board or internal clock.  This board is required whenever a T1 card is installed in the system. The 32.768MHz clock is provided to CGMD on MBU. It consists of a PLL circuit, PLL Monitoring circuit and clock (from T1 interface board) monitoring circuit.2